This invention relates to a non-volatile semiconductor memory device and, more particularly, it relates to a memory device adapted to store multi-valued data and also to a method of storing such data of the device.
NAND type flush memory devices comprising an EEPROM that is an electrically writable non-volatile semiconductor memory have been proposed. In such a NAND type flush memory, the sources and the drains of a plurality of adjacently arranged memory cells are connected in series and the plurality of memory cells that are connected in series are connected to a bit line as a unit. Then, a set of data are collectively written in or read from all or half of the plurality of cells arranged in a row.
In recent years, multi-valued memories that can store a plurality of data (n-bit data) written into a single cell have been developed as NAND type flush memories. Such a multi-valued memory requires the use of n latch circuits for writing data to or reading data from a single cell in order to write a plurality of data to or reading a plurality of data from the single cell because the threshold value of the cell is determined by the contents of the data latched by the latch circuits.
However, as the number of data n that can be stored in a single cell increases, the number of latch circuits that is equal to n also increases to make them occupy the chip that contains them to a large extent.
Meanwhile, when storing data in a cell, an operation is conducted to verify that the threshold value of the cell properly corresponds to the written data. The number of verifying operations increases as the number of data to be written to a cell. Then, the time required for data writing and write-verifying operations increases for each cell.
According to the invention, there is provided a method of storing data to a memory cell having n states (n being a natural number), the method including storing externally input data in a data storage circuit, executing one of shifting and holding a logic level of data which is stored in the data storage circuit in accordance with data read from the memory cell more than one time by varying a voltage supply to a gate electrode of the memory cell, and executing one of shifting and holding the states of the memory cell in accordance with the data which is stored in the data storage circuit.
According to the invention, there is also provided a method of storing data to a memory cell having n states (n being a natural number), the method including storing externally input data having one of a first logic level and second logic level in a data storage circuit, shifting a logic level of the data stored in the data storage circuit to the second logic level when data read from the memory cell is at the first logic level and the data stored in the data storage circuit is at the first logic level, shifting the logic level of the data stored in the data storage circuit to the first logic level when the data read from the memory cell is at the first logic level and the data stored in the data storage circuit is at the second logic level, holding the logic level of the data stored in the data storage circuit when the data read from the memory cell is at the second logic level, shifting a state of the memory cell when the logic level of the data stored in the data storage circuit is at the first logic level, and holding the state of the memory cell when the logic level of the data stored in the data storage circuit is at the second logic level.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.